Adlink ACL-8112 Series Manual do Utilizador descarregar pdf (Página 47)

Registers

•

4.10 Internal Timer/Counter Register

Two 8254 counters are used for periodical triggering of the A/D converter,

with one left for user applications. The 8254 occupies four I/O address

locations in the ACL-8112 as listed below. Users may refer to NEC's or Intel's

data sheet for full detail of the 8254. A summary of the information is

specified in Appendix B.

Address : BASE + 0 ~ BASE + 3

Attribute:

read / write

Data Format:

Base + 0 Counter 0 Register ( R/W)

Base + 1 Counter 1 Register ( R/W)

Base + 2 Counter 2 Register ( R/W)

Base + 3 8254 CONTROL BYTE

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 92 93

NuDAQ® 1
ACL-8112 Series 1
Enhanced Multi-Function 1
Data Acquisition Card 1
Getting Service from ADLINK 4
Table of Contents 5
How to Use This Guide 7
Introduction 9
Introduction 10
1.1 Features 11
1.2 Applications 12
1.3 Specifications 12
1.4 Software Support 16
Installation 17
2.2 Unpacking 18
2.3 ACL-8112's Layout 19
Installation 20
2.5 Base Address Setting 21
2.7 DMA Channel Setting 24
2.9 Clock Source Setting 26
2.10 IRQ Level Setting 26
Signal Connections 29
3.4 Digital I/O Connection 34
Connect with ACLD-8125 36
Connect with ACLD-9137 36
Connect with ACLD-9182 36
Connect with ACLD-9185 36
Connect with ACLD-9188 36
Registers 37
4.1 I/O Port Address 38
4.2 A/D Data Registers 39
4.8 Digital I/O register 45
4.9 D/A Output Register 46
Operation Theory 49
A/D Trigger Modes 50
A/D Data Transfer Modes 51
Vout Vref 52
5.4 Timer/Counter Operation 53
Calibration & Utilities 57
6.2 VR Assignment 58
6.3 D/A Adjustment 58
6.5 A/D Adjustment 59
C Language Library 61
7.1 _8112_Initial 62
Example: 63
7.2 _8112_Switch_Card_No 64
7.3 _8112_DI 65
7.4 _8112_DI _Channel 66
7.5 _8112_DO 67
7.6 _8112_DA 68
7.7 _8112_AD_Input_Mode 69
7.8 _8112_AD_Set_Channel 71
7.9 _8112_AD_Set_Range 72
Argument: 74
Return Code: 74
7.10 _8112_AD_Set_Mode 75
7.11 _8112_AD_Soft_Trig 77
7.12 _8112_AD_Aquire 78
7.13 _8112_CLR_IRQ 79
7.14 _8112_AD_DMA_Start 80
7.15 _8112_AD_DMA_Status 82
7.16 _8112_AD_DMA_Stop 83
7.17 _8112_AD_INT_Start 84
7.18 _8112_AD_INT_Status 85
7.19 _8112_AD_INT_Stop 86
7.20 _8112_AD_Timer 87
7.21 _8112_TIMER_Start 88
7.22 _8112_TIMER_Read 89
7.23 _8112_TIMER_Stop 89
Appendix A. Demo Programs 91
Warranty Policy 92

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