Adlink cPCI-6520 Manual do Utilizador

Advance Technologies; Automate the World.Manual Rev.: 2.01Revision Date: November 13, 2014Part No: 50-15086-1010cPCI-65206U CompactPCI® 3rd Generat

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88 BIOS SetupOut-of-Band Mgmt PortMicrosoft Windows emergency management services (EMS)allows for remote management of a Windows Server OSthrough a se

BIOS Setup 89cPCI-6520ParityThis is a display-only function providing information about theparity for Out-of-Band Management. Stop BitsThis is a disp

90 BIOS SetupCPU C3 ReportEnable or disable CPU C3 (ACPI C2) report to OS. Set this valueto Enabled/Disabled.CPU C6 ReportEnable or disable CPU C6 (AC

BIOS Setup 91cPCI-65208.4 Chipset SetupSelect the Chipset tab from the setup screen to enter the ChipsetBIOS Setup screen. You can select any of Chip

92 BIOS SetupPCI Express ConfigurationPCI Express Clock GatingEnable or disable XHCI Pre-Boot Driver support. Set this valueto Enabled/Disabled.DMI Li

BIOS Setup 93cPCI-6520USB ConfigurationXHCI Pre-Boot DriverEnable or disable XHCI Pre-Boot Driver support. Set this valueto Enabled/Disabled.XHCI Mod

94 BIOS SetupEHCI1/2Control the USB EHCI (USB 2.0) functions. One EHCI control-ler must always be enabled. Set this value to Enabled/Dis-abled.USB Por

BIOS Setup 95cPCI-6520Graphics ConfigurationPrimary DisplaySelect which graphics device should be the primary display.Set this value to Auto, IGFX, P

96 BIOS SetupDVMT Pre-AllocatedSelect DVMT 5.0 Pre-Allocated (fixed) graphics memory sizeused by the internal graphics device. Configuration options a

BIOS Setup 97cPCI-6520Memory ConfigurationMemory RemapEnable or disable memory remap above 4G. Set this value toEnabled/Disabled.

List of Tables xicPCI-6520List of TablesTable 2-1: cPCI-6520 Blade Specifications ... 9Table 2-2: cPCI-6520 I/O

98 BIOS Setup8.5 Boot SettingsSelect the Boot tab from the setup screen to enter the Boot BIOSSetup screen. You can select any of the items in the lef

BIOS Setup 99cPCI-6520Set Boot PrioritySet Boot Option #1 ~2 boot priority. Hard Disk Drive BBS PrioritiesSpecifies the boot device priority sequence

100 BIOS SetupLaunch Video OpROM policyThis option controls the execution of UEFI and Legacy VideoOpROM. Set this value to Do not launch, UEFI only, L

BIOS Setup 101cPCI-65208.6 Security SetupAdministrator, User PasswordIf only the administrator's password is set, then this only limitsaccess to

102 BIOS Setup8.7 Save & Exit MenuSelect the Save & Exit tab from the setup screen to enter the Save& Exit BIOS Setup screen. You can disp

BIOS Setup 103cPCI-6520Discard Changes and ResetReset system setup without saving any changes.Save ChangesSave changes done so far to any of the setu

104 BIOS SetupSave as User DefaultsSave the changes done so far as user defaults..Restore User DefaultsSave changes done so far to any of the setup op

Checkpoints & Beep Codes 105cPCI-65209 Checkpoints & Beep Codes9.1 Checkpoint Ranges9.2 Standard CheckpointsSEC PhaseStatus Code Range Descr

106 Checkpoints & Beep CodesSEC Beep Codes NonePEI Phase0x08 North Bridge initialization after microcode loading 0x09 South Bridge initialization

Checkpoints & Beep Codes 107cPCI-65200x1A Pre-memory South Bridge initialization (South Bridge module specific) 0x1B Pre-memory South Bridge init

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108 Checkpoints & Beep Codes0x3B Post-Memory South Bridge initialization is started 0x3C Post-Memory South Bridge initialization (South Bridge mod

Checkpoints & Beep Codes 109cPCI-65200xE3 OS S3 wake vector call 0xE4-0xE7 Reserved for future AMI progress codes S3 Resume Error Codes 0xE8 S

110 Checkpoints & Beep CodesPEI Beep CodesDXE Phase# of Beeps Description 1 Memory not Installed 1Memory was installed twice (InstallPeiMemory r

Checkpoints & Beep Codes 111cPCI-65200x6F North Bridge DXE initialization (North Bridge module specific) 0x70 South Bridge DXE initialization is

112 Checkpoints & Beep Codes0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is starte

Checkpoints & Beep Codes 113cPCI-6520DXE Beep Codes0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error

114 Checkpoints & Beep CodesACPI/ASL Checkpoints9.3 OEM-Reserved Checkpoint RangesStatus Code Description 0x01 System is entering S1 sleep state

Important Safety Instructions 115cPCI-6520Important Safety InstructionsFor user safety, please read and follow all instructions,WARNINGS, CAUTIONS,

116 Important Safety InstructionsX Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.A Lithium-type battery

Getting Service 117cPCI-6520Getting ServiceContact us should you require any service or assistance. ADLINK Technology, Inc. Address: 9F, No.166 Ji

Introduction 1cPCI-65201 Introduction1.1 OverviewThe cPCI-6520 is a 6U CompactPCI® processor blade in sin-gle-slot (4HP) width form factor featuring

118 Getting ServiceADLINK Technology, Inc. (French Liaison Office) Address: 6 allée de Londres, Immeuble Ceylan 91940 Les Ulis, France Tel: +3

2IntroductionThe cPCI-6520 supports operation in both a system slot and in aperipheral slot as a standalone blade. The cPCI-6520 is compliantwith the

Introduction 3cPCI-65201.2 FeaturesX 6U CompactPCI® processor blade in 4HP width form factorX Supports FCBGA package 4-core 3rd Generation Intel® Cor

4Introduction1.3 Block DiagramFigure 1-1: cPCI-6520 Functional Block DiagramFront Panel DMI J1/J2 J3/J4/J5 PCIe x8 Gen3 PCIe x4 PI7C9X130CF PCIe x4

Introduction 5cPCI-65201.4 Product ListProducts included in the cPCI-6520 are:Processor BladeX cPCI-6520: 4HP width (single-slot) 6U CompactPCI blade

6Introduction1.5 Package Contents The cPCI-6520 is packaged with the following components. If anyof the items on the contents list are missing or dama

Introduction 7cPCI-6520NOTE:NOTE:The contents of non-standard cPCI-6520 configurations may vary depending on the customer requirements.CAUTION:This p

Revision HistoryRevision Release Date Description of Change(s)2.00 2013/03/13 Initial release2.01 2014/11/13 Add PMC slot -12V support note

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Specifications 9cPCI-65202 Specifications2.1 cPCI-6520 Blade SpecificationsCompactPCI® Standards• PICMG® 2.0 CompactPCI® Rev. 3.0• PICMG® 2.1 Hot Swa

10 SpecificationsGigabit Ethernet• One front panel GbE LAN port from Intel® 82579LM PHY controller and one front panel GbE LAN from Intel 82574 Gigabi

Specifications 11cPCI-6520Notes:1. The SATA direct connector is removable (DB-LSATA) and canbe replaced with a CFast socket adapter. A CFast card and

12 Specifications2.2 I/O ConnectivityTable 2-2: cPCI-6520 I/O ConnectivityNotes:1. Signals are passed through to the RTM. Available functions aredepe

Specifications 13cPCI-65202.3 Power RequirementsIn order to guarantee a stable functionality of the system, it is rec-ommended to provide more power

14 SpecificationsPower ConsumptionThis section provides information on the power consumption of thecPCI-6520 when using Intel® Core™ i7 processors wit

Functional Description 15cPCI-65203 Functional DescriptionThe following sections describe the cPCI-6520 features andfunctions.3.1 ProcessorsThe 3rd G

16 Functional DescriptionSupported TechnologiesX Intel® Virtualization Technology for Directed I/O (Intel® VT-d)X Intel® Virtualization Technology (In

Functional Description 17cPCI-65203.2 ChipsetThe cPCI-6520 incorporates the Intel® QM77 Platform ControllerHub (PCH).Intel® QM77 Platform Controller

Preface iiicPCI-6520PrefaceCopyright 2013 ADLINK Technology Inc.This document contains proprietary information protected by copy-right. All rights ar

18 Functional Description3.3 PMC/XMC SiteThe cPCI-6520 supports one PMC or XMC site for front panel I/Oexpansion. The PMC site provides a maximum 32/6

Functional Description 19cPCI-65203.6 Intel® Active Management TechnologyIntel® Active Management Technology (Intel® AMT) is a hardwarebased technolo

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Board Interfaces 21cPCI-65204 Board Interfaces4.1 cPCI-6520 Board LayoutFigure 4-1: cPCI-6520 Board LayoutBT2 Battery JN1/2/3/4 PMC connectorsCN1 SOD

22 Board Interfaces4.2 cPCI-6520 Assembly LayoutFigure 4-2: cPCI-6520 Assembly LayoutOnboard2.5" DriveDB-LSATA

Board Interfaces 23cPCI-65204.3 cPCI-6520 Front PanelFigure 4-3: cPCI-6520 Front PanelStatus LEDsGeneral Purpose LEDsIn default mode, these eight LED

24 Board Interfaces4.4 Connector Pin AssignmentsSee “cPCI-6520 Board Layout” on page 21 for connector locations.Front Panel ConnectorsGigabit Ethernet

Board Interfaces 25cPCI-6520COM1 (RJ-45)COM1 RJ-45 to DB-9 CablePin # RS-232 RS-422 RS-4851 DCD# TX- Data-2RTS# — —3DSR# — —4TXD RX+ —5 RXD TX+ Data+

26 Board InterfacesUSB 3.0 ConnectorsDisplayPort Connectors (DP1, DP2)*Pin # Signal Name1VCC2 Data-3 Data+4GND5RX_N6RX_P7GND8TX_N9TX_PPin # Signal Pin

Board Interfaces 27cPCI-6520Onboard ConnectorsSATA Connector (CN10)SATA Connector on DB-LSATAPin # Signal1GND2TXP3TXN4GND5RXN6RXP7GNDPin # SignalS1 G

iv PrefaceUsing this ManualAudience and ScopeThe cPCI-6520 User’s Manual is intended for hardwaretechnicians and systems operators with knowledge of i

28 Board InterfacesCFast Socket (on DB-CFast)Pin # Signal NameGround S1SATA_TX-P S2SATA_TX-N S3Ground S4SATA_RX-N S5SATA_RX-P S6Ground S7CFast_CDI P1G

Board Interfaces 29cPCI-6520DB-LSATA Connector (CN9)Signal Name Pin # Pin # Signal NameGND 1 2 GNDGND 3 4 GNDGND 5 6 GNDGND 7 8 GNDGND 9 10 GNDGND 11

30 Board InterfacesPMC Connector (JN1, JN2, JN3, JN4)*Note: -12V signal not supported on JN1 pin 2. Contact ADLINK for moreinformation.Pin# JN1 Signal

Board Interfaces 31cPCI-6520PMC Connector Pin Definition (cont’d)Pin# JN1 Signal JN2 Signal JN3 Signal JN4 Signal33 PCIX_FRAME-L GND GND PIO3334 GND

32 Board InterfacesXMC Connector (CN2)Pin# A B C D E F1RXP RXN 3.3V NC NC VPWR2GND GND Not used GND GND PCIE_RST-L3NC NC 3.3V NC NC VPWR4GND GND Not u

Board Interfaces 33cPCI-6520CompactPCI J1 Connector Pin AssignmentPin Z A B C D E F25 GND +5V REQ64# ENUM# +3.3V +5V GND24 GND AD1 +5V V(I/O) AD0 ACK

34 Board InterfacesCompactPCI J2 Connector Pin AssignmentPin Z A B C D E F22 GND GA4 GA3 GA2 GA1 GA0 GND21 GND CLK6 GND NC NC NC GND20 GND CLK5 GND NC

Board Interfaces 35cPCI-6520CompactPCI J3 Pin AssignmentPin Z A B C D E F19 GND P5V P5V P12V P5V P5V GND18 GND LAN3_TXD1+ LAN3_TXD0- GND LAN3_TXD2+ L

36 Board InterfacesCompactPCI J4 Connector Pin AssignmentPin Z A B C D E F25 GND PMC IO:P1 PMC IO:N1 NC PMC IO:P2 PMC IO:N2 GND24 GND PMC IO:P3 PMC IO

Board Interfaces 37cPCI-6520CompactPCI J5 Pin AssignmentPin Z A B C D E F22 GND Power LEDLAN2_LINK_ACT# LAN2_VCC_TERM LAN3_LINK_ACT# LAN3_VCC_TERMGND

Preface vcPCI-6520ConventionsTake note of the following conventions used throughout thismanual to make sure that users perform certain tasks andinstr

38 Board Interfaces4.5 Switches and ButtonsSee “cPCI-6520 Front Panel” on page 23 and “cPCI-6520 BoardLayout” on page 21 for switch locations.System R

Board Interfaces 39cPCI-6520IPMC Mode Switch (SW_MOD1)Switch SW_MOD1 is a multi purpose switch that allows users todefine the blade operating mode. A

40 Board InterfacesPMC Frequency Switch (SW_PMC1)Switch SW_PMC1 sets the frequency and mode of the PMCslot. All are set to OFF by default..PMC VIO Fun

Board Interfaces 41cPCI-6520SW_IPMCDEG1Switch SW_IPMCDEG1 is for debugging purposes and shouldbe left in the default setting of “All OFF”.Reserved Sw

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Getting Started 43cPCI-65205 Getting StartedThis chapter describes the installation of the following componentsto the cPCI-6520 and rear transition m

44 Getting StartedInstalling a CF card1. A CompactFlash can be installed in the location markedbelow.2. Turn the blade over (solder side up). Unscrew

Getting Started 45cPCI-65203. Turn the blade over (component side up), then align andinsert the CompactFlash card into the slot until it is prop-erly

46 Getting Started5. The CompactFlash card installation is completed.Removing a CF card with SATA Drive installedTo remove a CompactFlash card, revers

Getting Started 47cPCI-65202. Remove the screw securing the CompactFlash bracketto the drive assembly as marked below.3. Remove the CompactFlash card

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48 Getting Started5.3 SATA Drive InstallationThe cPCI-6520 provides space to install a slim type 2.5” SATAdrive. Installing a SATA Drive - cPCI-65201.

Getting Started 49cPCI-65203. Secure the drive to the bracket by fastening the fourscrews provided in the package in the locations markedbelow.4. Ali

50 Getting Started5. Secure the drive bracket by securing a screw at the CFbracket through to the drive bracket shown as below.6. Turn the blade over

Getting Started 51cPCI-65205.4 PMC/XMC InstallationThe cPCI-6520 series provides space to install a PMC or XMCmodule. 1. A PMC/XMC mezzanine card can

52 Getting Started3. Align the connectors on the PMC/XMC module to thePMC/XMC connectors on cPCI-6520 blade. Press downto secure the PMC/XMC module to

Getting Started 53cPCI-65205.5 CFast Card installationThe cPCI-6520 Series provides space to install a CFast card(optional accessory P/N: 91-37572-00

54 Getting Started3. 3.The CFast adapter with card can be installed at theSATA connector location as indicated below.4. 4.Flip the CFast adapter so th

Getting Started 55cPCI-65205. 5.Secure the CFast adapter with two screws as shownbelow.

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Driver Installation 57cPCI-65206 Driver InstallationThe cPCI-6520 drivers are available from the ADLINK All-In-OneDVD at X:\cPCI\cPCI-6520\, or from

Table of Contents viicPCI-6520Table of ContentsRevision History... iiPreface...

58 Driver Installation9. Install the TPM utilities by extracting and running theprogram in …\TPM\ Atmel_TPM_Dvr_WinXP_32_64_4-0-0-msi.zip.10.Install t

Utilities 59cPCI-65207 Utilities7.1 Watchdog TimerThis section describes the operation of the cPCI-6520’s watchdogtimer (WDT). The primary function o

60 UtilitiesSample CodeThe sample program written in C shown below offers an interac-tive way to test the Watchdog Timer under DOS.#include<stdio.h

Utilities 61cPCI-6520tempCount = count_value / 60;if((count_value%60) > 30)tempCount++;if(tempCount > 255)tempCount = 255;printf("WDT time

62 UtilitiesregisterValue |= 0x02; // set GPIO2 is activeoutportb(W83627UHG_ioPort+1, registerValue);outportb(W83627UHG_ioPort, 0xe4);registerValue =

Utilities 63cPCI-6520registerValue = inportb(W83627UHG_ioPort+1);registerValue |= 0x08; // set GPIO23 is Highoutportb(W83627UHG_ioPort+1, registerVal

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BIOS Setup 65cPCI-65208 BIOS SetupThe following chapter describes basic navigation for theAMIBIOS®8 BIOS setup utility.8.1 Starting the BIOSTo enter

66 BIOS SetupSetup MenuThe main BIOS setup menu is the first screen that you can navi-gate. Each main BIOS setup menu option is described in thisuser’

BIOS Setup 67cPCI-6520The < F8 > key on your keyboard is the Fail-Safe key. It is not dis-played on the key legend by default. To set the Fail-

viii Table of Contents4.2 cPCI-6520 Assembly Layout... 224.3 cPCI-6520 Front Panel ...

68 BIOS SetupF2 The < F2 > key on your keyboard is the previous values key. It is not displayed on the key legend by default. To set the previou

BIOS Setup 69cPCI-6520Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key to select Cancel and

70 BIOS Setup8.2 Main SetupWhen you first enter the Setup Utility, you will enter the Main setupscreen. You can always return to the Main setup screen

BIOS Setup 71cPCI-65208.3 Advanced BIOS SetupSelect the Advanced tab from the setup screen to enter theAdvanced BIOS Setup screen. You can select any

72 BIOS Setup8.3.1 PCI Subsystem SettingsYou can use this screen to select options for the PCI SubsystemSettings. Use the up and down < Arrow >

BIOS Setup 73cPCI-6520VGA Palette SnoopEnables or disables VGA Palette Registers Snooping. Set thisvalue to Disabled/Enabled.PERR# GenerationEnables

74 BIOS SetupACPI Sleep StateSelect the highest ACPI sleep state the system will enter, whenthe SUSPEND button is pressed. Set this value to S1 only,

BIOS Setup 75cPCI-6520Security Device SupportOS will not show TPM. Reset of platform is required. Set this valueto Enabled/Disabled.TPM StateDetermin

76 BIOS Setup8.3.4 CPU ConfigurationYou can use this screen to select options for the CPU Configura-tion Settings. Use the up and down < Arrow >

BIOS Setup 77cPCI-6520Limit CPUID MaximumWhen the computer is booted up, the operating system executesthe CPUID instruction to identify the processor

List of Figures ixcPCI-6520List of FiguresFigure 1-1: cPCI-6520 Functional Block Diagram... 4Figure 4-1: cPCI-6520 Board L

78 BIOS Setup8.3.5 SATA ConfigurationYou can use this screen to select options for the SATA Configura-tion Settings. An example of the SATA Configurat

BIOS Setup 79cPCI-6520External SATA PortAppears when SATA mode is AHCI. eSATA port support. Set thisvalue to Enabled/Disabled.Hot PlugAppears when SA

80 BIOS Setup8.3.6 Intel TXT(LT) ConfigurationYou can use this screen to select options for the Intel TXT(LT)Configuration Settings. An example of the

BIOS Setup 81cPCI-65208.3.7 AMT ConfigurationYou can use this screen to select options for the AMT settings.Use the up and down < Arrow > keys

82 BIOS Setup8.3.8 USB ConfigurationYou can use this screen to select options for the USB Configura-tion. Use the up and down < Arrow > keys to

BIOS Setup 83cPCI-6520EHCI Hand-offThis is a workaround for OSes without EHCI hand-off support. TheEHCI ownership change should be claimed by the EHC

84 BIOS Setup8.3.10 Hardware MonitorThis option displays the current status of all of the monitored hard-ware devices/components such as voltages and

BIOS Setup 85cPCI-65208.3.11 Serial Port Console RedirectionYou can use this screen to select options for the serial port con-sole redirection settin

86 BIOS SetupTerminal TypeVT100+ is the preferred terminal type for out-of-band manage-ment. Configuration options: VT100, VT100+, VT-UTF8, ANSI. Bits

BIOS Setup 87cPCI-6520Flow Control Set this option to select Flow Control for console redirection.The settings for this value are None, Hardware RTS/