Adlink LPCIe-3488A Manual do Utilizador descarregar pdf (Página 36)

26 Operations

3.2 Block Diagrams

ADLINK GPIB Interface Cards

The ADLINK LPCIe-3488A FPGA includes a 2kB FIFO to maxi-

mize data transfer rate, coordinating data flow between the PCIe

bus, FIFO and GPIB bus.

Figure 3-2: LPCIe-3488A Block Diagram

ADLINK’s LPCI-3488A GPIB interface card includes a 2 kB FIFO

inside the FPGA IP to maximize data transfer rates. Its

state-of-the-art state machine in the CPLD coordinates the data

flow between the PCI controller, FIFO and GPIB bus.

Figure 3-3: LPCI-3488A Block Diagram

Bus

Transceiver/

Receiver

GPIB IP

FPGA

PCIe IP2K FIFO

PCIe x1

Interface

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Adlink LPCIe-3488A Manual do Utilizador Página 36