Adlink PCI-7300A Manual do Utilizador

NuIPC / NuDAQ cPCI-7300A & PCI-7300A 80MB Ultra-High Speed 32-CH Digital I/O Boards User’s Guide Recycle Paper

2 • Introduction 1.1 Applications • Interface to high-speed peripherals • High-speed data transfers from other computers • Automated test equipme

Introduction • 3 1.3 Specifications ♦ Digital I/O (DIO) • Numbers of Channel: 32 TTL compatible inputs and/or outputs • Device: IDT 74FCT373 • I

4 • Introduction • Mode: Bus Mastering DMA with Scatter/Gather • Data Transfers: 8/16/32-bit input or output (programmable) ♦ DMA Transfer count:

Introduction • 5 1.4 Software Supporting ADLINK provides versatile software drivers and packages for users’ different approach to built-up a system.

6 • Introduction 1.4.3 PCIS-VEE: HP-VEE Driver The PCIS-VEE includes the user objects, which are used to interface with HP VEE software package. PC

Installation • 7 2 Installation This chapter describes how to install the cPCI/PCI-7300A. At first, the contents in the package and unpacking informa

8 • Installation 2.2 Unpacking Your cPCI/PCI-7300A card contains sensitive electronic components that can be easily damaged by static electricity. T

Installation • 9 2.4 PCI-7300A's Layout Figure 2.1 PCI-7300A Layout Diagram

10 • Installation Figure 2.2 cPCI-7300A Layout Diagram

Installation • 11 2.5 Hardware Installation Outline PCI configuration The PCI cards (or CompactPCI cards) are equipped with plug and play PCI contro

Copyright 2002 ADLINK Technology Inc. All Rights Reserved. Manual Rev 2.22: July 16, 2002 Part No.: 50-11106-100 The information in this docume

12 • Installation 2.6 Connector Pin Assignment The PCI-7300A comes equipped with one 100-pin SCSI type connector (CN1) located on the rear mounting

Installation • 13 Figure 2.2 CN1 Pin Assignment GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GN

14 • Installation 2.7 Wiring and Termination Transmission line effects and environment noise, particularly on clock and control lines, can lead to

Installation • 15 2.8 Daughter Board Supporting The cPCI/PCI-7300A can be connected with two daughter boards: DIN-100S or DIN-502S. The functionali

16 • Registers 3 Registers In this chapter, the registers’ format of the cPCI/PCI-7300A is described. Please note that the registers’ map of the PCI

Registers • 17 3.1 I/O Port Base Address The registers of the cPCI/PCI-7300A are shown in Table 3.1. The base address of these registers is als o a

18 • Registers 3.2 DI_CSR: DI Control & Status Register Digital input control and status checking is done by this register. Address: BASE + 00

Registers • 19 DI_FIFO_CLR (R/W) 0: No effect 1: Clear digital input FIFO. If both PORTA and PORTB are configured as inputs, both FIFO will be cle

20 • Registers DO_WAIT_NAE (R/W) 0: do not wait output FIFO not almost empty flag 1: delay output data until FIFO is not almost empty PAT_GEN(R/W)

Registers • 21 BURST_HNDSHK (R/W) 0: disable burst handshaking mode 1: enable burst handshake mode * Note: This bit is for Rev.B only. 3.4 Auxilia

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22 • Registers T2_EN (R/W) 0: Disable Timer2 interrupt 1: Interrupt CPU on falling edge of Timer 2 output AUXDI0_INT (R/W) 0: AUXDI does not genera

Registers • 23 3.7 DO_FIFO: DO external data FIFO direct access port The digital output FIFO data can be accessed through this port directly. Add

24 • Registers 3.8 FIFO_CR: FIFO almost empty/full register The register is used to control the FIFO programmable almost empty/full flag. Address

Registers • 25 DI_ACK_NEQ (R/W) 0: DI_ACK is rising edge active 1: DI_ACK is falling edge active DI_TRG_NEQ (R/W) 0: DI_TRG is rising edge active

26 • Operation Theory 4 Operation Theory This chapter provides the detailed operation information for the cPCI/PCI-7300A, including I/O configuration

Operation Theory • 27 Notes: PORTA is default as Input channel; PORTB is default as output channel. In DI32 mode, the PORTB has to be configured as t

28 • Operation Theory AUX DI 3..0: Four auxiliary digital inputs DITRIG: Digital input trigger line DIACK/DIREQ: Digital input handshaking signals

Operation Theory • 29 4.4 Input FIFO and Output FIFO Due to the data transfer rate between external devices and the cPCI/PCI-7300A is independent fr

30 • Operation Theory 4.5 Bus-mastering DMA Digital I/O data transfer between PCI-7300A and PC’s system memory is through bus mastering DMA, which i

Operation Theory • 31 4.6 Scatter/gather DMA The PCI Bridge also supports the function of scatter/gather bus mastering DMA, which helps the users to

32 • Operation Theory In non-chaining mode, the maximum DMA data transfer size is 2M double words (8M bytes). However, by using chaining mode, scatt

Operation Theory • 33 for the assertion of DI-ACK. If the external device follows the rule, there would be no data lost due to FIFO overrun. 3. Ha

34 • Operation Theory 2. WaitTRIG: The data transfer will not start until external trigger signal (DI-TRIG for digital input, DO-TRIG for digital ou

Operation Theory • 35 4. Define the starting mode to be NoWait or WaitTRIG. 5. The digital input data are stored in the input FIFO after a DI comman

36 • Operation Theory Notes: When the DMA function of digital input starts, the input data will be stored in the FIFO of the cPCI/PCI-7300A. The data

Operation Theory • 37 The operation flow is show as below: The followings are timing diagrams of the DI-REQ and the input data. The active edge o

38 • Operation Theory DIREQ as input data strobe (when Falling Edge Active) Notes: From the timing diagram of external clock mode, the maximum frequ

Operation Theory • 39 8. The data saved in FIFO will transfer to system memory of your computer directly and automatically by bus mastering DMA. The

40 • Operation Theory 4.10.4 Continuous Digital Input If the digital input operation still active after the competition of the previous DMA transfer

Operation Theory • 41 Notes: The latency time between two DMA transfers is different from the PCI bus latency time mentioned in the previous section

Table of Contents • i Table of Contents Introduction...1 1.1 APPLICATIONS

42 • Operation Theory As the data output in the internal clock mode, the DOREQ signal could be use as the output strobe to indicate the output operat

Operation Theory • 43 The operation flow is show as below: The timing diagram of the DOREQ and DOACK in the DO handshaking mode is shown as follows

44 • Operation Theory 4.11.3 Digital Output DMA in Burst Handshaking Mode The burst handshaking mode is a fast and reliable data transfer protocol.

Operation Theory • 45 The operation flow is show as below: Notes: When the DMA function of digital output starts, the output data will transfer to

46 • Operation Theory 4. Set the output patterns into the output FIFO by direct FIFO access 5. Start the pattern generator function. 6. The pattern g

C/C++ Libraries • 47 5 C/C++ Libraries This chapter describes the software library for operating this card. Only the functions in DOS library and Win

48 • C/C++ Libraries 5.2 Programming Guide 5.2.1 Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver

C/C++ Libraries • 49 5.3 _7300_Initial @ Description A PCI-7300A card is initialized according to the card number. Because the cPCI/PCI-7300A is PCI

50 • C/C++ Libraries 5.4 _7300_Close @ Description Close a previously initialized PCI-7300A card. @ Syntax Visual C/C++ (Windows 95) int W_7300_Clos

C/C++ Libraries • 51 DI8DO16: PORTA is 8 -bit input and PORTB is 16-bit output DI16DO8: PORTA is 16-bit input and PORTB is 8 -bit output DI16DO

ii • Table of Contents 4.3 DIGITAL I/O DATA FLOW ...28 4.4 INPUT FIFO AND O

52 • C/C++ Libraries 5.6 _7300_DI_Mode @ Description Set the clock mode and start mode for the PCI-7300A DI operation. @ Syntax Visual C/C++ (Window

C/C++ Libraries • 53 5.7 _7300_DO_Mode @ Description Set the clock mode and start mode for the PCI-7300A DO operation. @ Syntax Visual C/C++ (Window

54 • C/C++ Libraries 5.8 _7300_AUX_DI @ Description Read data from auxiliary digital input port. You can get all 4 bits input data by using this fun

C/C++ Libraries • 55 card_number: The card number of the PCI-7300A card. di_ch_no: the DI channel number, the value has to be set within 0 and 3.

56 • C/C++ Libraries @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DO_Channel (int card_number, int do_ch_no, int do_data) Visual Basic (Windows

C/C++ Libraries • 57 @ Return Code NoError AllocDMAMemFailed 5.13 _7300_Free_DMA_Mem @ Description Deallocate a system DMA memory under Windows 95

58 • C/C++ Libraries use an 8237-style DMA controller in the host computer and therefore it is not blocked in 64K maximal groups. PCI-7300A bus maste

C/C++ Libraries • 59 @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Start (int card_number, HANDLE memID, U32 count, int clear_fifo, int disabl

60 • C/C++ Libraries @ Return Code NoError PCICardNumErr PCICardNotInit DMATransferNotAllowed InvalidDIOCount BufNotDWordAlign DMADscrBadAlign 5.15

C/C++ Libraries • 61 int _7300_DI_DMA_Stop (int card_number) @ Argument card_number: The card number of the PCI-7300A card. @ Return Code NoError P

Table of Contents • iii 5.19 _7300_DO_DMA_STATUS...63 5.20 _7300_DO_DMA_ABORT...

62 • C/C++ Libraries int W_7300_DO_DMA_Start (int card_number, HANDLE memID, U32 count) Visual Basic (Windows 95) W_7300_DO_DMA_Start (ByVal card_num

C/C++ Libraries • 63 5.19 _7300_DO_DMA_Status @ Description Since the _7300_DO_DMA_Start function is executed in background, you can issue the fu

64 • C/C++ Libraries PCICardNumErr PCICardNotInit 5.21 _7300_DO_PG_Start @ Description The function will perform pattern generation with the dat

C/C++ Libraries • 65 5.22 _7300_DO_PG_Stop @ Description This function is used to stop the pattern generation operation. After executing this fun

66 • C/C++ Libraries @ Return Code NoError PCICardNumErr PCICardNotInit 5.24 _7300_DO_Timer @ Description This function is used to set the intern

C/C++ Libraries • 67 W_7300_Int_Timer (ByVal card_number As Long, ByVal c2 As Integer) As Long C/C++ (DOS) int _7300_Int_Timer (int card_number, U16

68 • C/C++ Libraries 5.27 _7300_Set_Sample @ Description For the language without pointer support such as Visual Basic, programmer can use this f

C/C++ Libraries • 69 @ Argument card_number: The card number of the PCI-7300A card. underrun: 0: underrun sitation did not occur. 1: underrun sit

70 • Appendix A 8254 Programmable Interval Timer Appendix A 8254 Programmable Interval Timer Note: The material of this section is adopted from “I

Appendix A 8254 Programmable Interval Timer • 71 Before loading or reading any of these individual counters, the control byte (Base + C) must be loa

How to Use This Guide • iv How to Use This Guide This manual is designed to help you use the cPCI-7300 and PCI-7300A Rev.B. The manual describes how

72 • Appendix A 8254 Programmable Interval Timer A.3 Mode Definition In 8254, there are six different operating modes can be selected. They are: •

Appendix A 8254 Programmable Interval Timer • 73 • Mode 3: Square Wave Rate Generator. Similar to MODE 2 except that the output will remain high un

74 • Warranty Policy Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please

Warranty Policy • 75 5. To ensure the speed and quality of product repair, please download an RMA application form from our company website www.ad

Introduction • 1 1 Introduction The cPCI/PCI-7300A is cPCI/PCI form factor ultra-high speed digital I/O card, it consists of 32 digital input or outp