Adlink PCI-7256 Manual do Utilizador descarregar pdf (Página 28)

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3.7 Interrupt Control Register

There are two different interrupt modes in PCI-7256. In the first mode, users

enable the COS interrupt function to monitor the enabled input channel’s

status whenever the status changes from 0 to 1 or 1 to 0. In the second

mode, users can select digital input channel 0, channel 1 or both channels as

the interrupt sources. In this mode, interrupt only assertes when the DI status

changes from 0 to 1, i.e., rising edge.

Because the two different modes

share the same interrupt signal in hardware, users are not allowed to

enable these two modes at the same time.

After processing the interrupt request event, users have to clear the interrupt

request in order to handle another interrupt request. To clear the interrupt

request, write 1 to the corresponding bit.

Address: BASE + 0x08

Attribute: Write

7 6 5 4 3 2 1 0

--- --- --- --- ---

CH1

CLR

CH0

CLR

COS

CLR

15 14 13 12 11 10 9 8

--- --- --- --- ---

CH1

Int_EN

CH0

Int_EN

COS

Int_EN

COS CLR (bit 0): write 1 to clear the COS interrupt.

1 : clear the COS interrupt

0 : no effect

CH0 CLR (bit 1): write 1 to clear DI channel 0 interrupt.

1 : clear DI channel 0 interrupt

0 : no effect

CH1 CLR (bit 2): write 1 to clear DI channel 1 interrupt.

1 : clear DI channel 1 interrupt

0 : no effect

COS Int_EN (bit 8): Write/Read

Change-of-State interrupt enable control

1 : enable

0 : disable

CH0 Int_EN (bit 9): Write/Read

DI channel 0 interrupt enable control

1 : enable

0 : disable

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 47 48

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