Adlink PCI-7256 Manual do Utilizador descarregar pdf (Página 30)

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3.8 Interrupt Status Register

When interrupt occurs, this register provides information for users to

recognize the interrupt status and the interrupt setup condition.

Address: BASE + 0x08

Attribute: Read

7 6 5 4 3 2 1 0

--- --- --- --- ---

CH1 Int.

Status

CH0 Int.

Status

COS

Int.

Status

15 14 13 12 11 10 9 8

--- --- --- --- ---

CH1

Int_EN

CH0

Int_EN

COS

Int_EN

COS Int. Status (bit 0): COS interrupt Status register

0: COS interrupt de-asserts

1: COS interrupt asserts

CH0 Int. Status (bit 1): Digital input channel 0 interrupt status

0: Ch0 interrupt de-asserts

1: Ch0 interrupt asserts

CH1 Int. Status (bit 2): Digital input channel 1 interrupt status

0: Ch1 interrupt de-asserts

1: Ch1 interrupt asserts

3.9 Handling PCI Controller Registers

The PCI bus controller adopted in PCI-7256 is PCI-9030 which is provided by

PLX technology Inc. When users attempt to handle low-level programming,

some registers in PCI-9030 should be noticed. The interrupt control

information from local bus to PCI bus. When users want to develop their own

interrupt function driver, both interrupt registers in PCI-9030 and in PCI-7256

have to work together. For more detailed information about the interrupt

control register in PCI-9030, please refer to the PCI-9030 databook.

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Adlink PCI-7256 Manual do Utilizador Página 30