Adlink Express-HLE Manual do Utilizador descarregar pdf (Página 35)

Express-HLE Page 35

4.3 XDP Debug header

The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation

resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.

Pin XDP Signal Target Signal I/O Device Pin XDP Signal Target Signal I/O Device

1 GND GND NA 2 GND GND NA

3 OBSFN_A0 PREQ# I/O processor 4 OBSFN_C0 CFG[17]

I processor

5 OBSFN_A1 PRDY# I/O processor 6 OBSFN_C1 CFG[16]

I processor

7 GND GND NA 8 GND GND NA

9 OBSDATA_A0 CFG[0]

I/O processor 10 OBSDATA_C0 CFG[8]

I/O processor

11 OBSDATA_A1 CFG[1]

I/O processor 12 OBSDATA_C1 CFG[9]

I/O processor

13 GND GND NA 14 GND GND NA

15 OBSDATA_A2 CFG[2]

I/O processor 16 OBSDATA_C2 CFG[10]

I/O processor

17 OBSDATA_A3 CFG[3]

I/O processor 18 OBSDATA_C3 CFG[11]

I/O processor

19 GND GND NA 20 GND GND NA

21 OBSFN_B0 BPM#[0]

I/O processor 22 OBSFN_D0 CFG[19]

I/O processor

23 OBSFN_B1 BPM#[1]

I/O processor 24 OBSFN_D1 CFG[18]

I/O processor

25 GND GND NA 26 GND GND NA

27 OBSDATA_B0 CFG[4]

I/O processor 28 OBSDATA_D0 CFG[12]

I processor

29 OBSDATA_B1 CFG[5]

I/O processor 30 OBSDATA_D1 CFG[13]

I processor

31 GND GND NA 32 GND GND NA

33 OBSDATA_B2 CFG[6]

I/O processor 34 OBSDATA_D2 CFG[14]

I/O processor

35 OBSDATA_B3 CFG[7]

I/O processor 36 OBSDATA_D3 CFG[15]

I/O processor

37 GND GND NA 38 GND GND NA

39 HOOK0 PWRGOOD I system 40 ITPCLK/HOOK4 Open NA

41 HOOK11 BP_PWRGD_RST# O system 42 ITPCLK#/HOOK5 Open NA

43 VCC_OBS_AB VCCIO_OUT I system 44 VCC_OBS_CD VCCIO_OUT I system

45 HOOK2 PWR_DEBUG O processor 46 HOOK6/RESET# PLTRSTIN# I system

47 HOOK3 PCH_SYS_PWROK O system 48 HOOK7/DBR# DBR# O system

49 GND GND NA 50 GND GND NA

51 SDA1 SDA I/O system 52 TDO TDO I processor

53 SCL1 SCL I/O system 54 TRSTn TRST# O processor

55 TCK1 Open NA 56 TDI TDI O processor

57 TCK0 TCK O processor 58 TMS TMS O processor

59 GND GND NA 60 GND G ND (or XDP_

PRESENT# if required)

Notes:

1. These signals are optional, can be left as OPEN/No-Connect if debug by Intel will not be needed.

2. These CFG signals can be left as Open/No Connect if not used as a strapping signal and top side probe will be used to debug

processor.

Refer to the "Shark Bay and Denlow Platforms Debug Port Design Guide (DPDG)", Document Number: 479493, Revision: 1.2

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 88 89

Comentários a estes Manuais

Sem comentários

Adlink Express-HLE Manual do Utilizador Página 35

Comentários a estes Manuais

Manuais e produtos relacionados com Hardware Adlink Express-HLE