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Signal Connections 21

3 Signal Connections

This chapter describes DAQ-/DAQe-/PXI-2016/2010/2006/2005

card connectors and the signal connection between the DAQ-/

DAQe-/PXI-2016/2010/2006/2005 card and external devices.

3.1 Connectors Pin Assignment

The DAQe-/PXI-2016/2010/2006/2005 card is equipped with one

68-pin VHDCI-type connector (AMP-787254-1). It is used for digi-

tal input/output, analog input/output, timer/counter signals, etc.

One 20-pin ribbon male connector is used for SSI (System Syn-

chronous Interface) in DAQ-2016/2010/2006/2005 card. The pin

assignments of the connectors are defined in Table 3-1 and

Table 3-2.

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 91 92

DAQ-/DAQe-/PXI 1
2016/2010/2006/2005 1
Getting service 3
Using this manual 5
1.3 Conventions 6
Table of Contents 7
List of Tables 9
List of Figures 10
List of Figures v 11
1 Introduction 13
1.1 Features 14
1.2 Applications 15
1.3 Specifications 16
System Noise: (Typical) 17
Gain error: 20
2005/2006/2016 20
Ω typical 21
10 Introduction 22
Ω for DAQ-/DAQe-/PXI-2010 23
°C to 55°C 24
°C to 80°C 24
1.4 Software Support 25
DAQ-LVIEW PnP: LabVIEW Driver 26
D2K-OCX: ActiveX Controls 26
2 Installation 27
16 Installation 28
2.3 Card Layout 29
DAQ-2016/2010/2006/2005 30
PXI-2016/2010/2006/2005 30
2.4 PCI Configuration 31
20 Installation 32
3 Signal Connections 33
VHDCI-type (68-pin) Connector 34
*PIO means programmable I/O 36
SSI Connector (J3) 37
Types of signal sources 38
Single-Ended Measurements 38
Differential Measurements 39
28 Signal Connections 40
4 Operation Theory 41
34 Operation Theory 46
Ch1 with unipolar ±10V 46
Ch2 with bipolar ±2.5V 46
Ch4 with bipolar ±1.25V 46
36 Operation Theory 48
Figure 4-3: Scan Timing 48
Trigger Modes 49
PSC_counter = 0 50
Operation Theory 39 51
40 Operation Theory 52
Operation Theory 41 53
Figure 4-9: Middle-Trigger 53
42 Operation Theory 54
Figure 4-10: Post trigger 54
Operation Theory 43 55
Figure 4-11: Delay trigger 55
44 Operation Theory 56
Operation Theory 45 57
46 Operation Theory 58
4.2 D/A Conversion 59
Software Update 60
Timed Waveform Generation 61
50 Operation Theory 62
52 Operation Theory 64
Operation Theory 53 65
DLY2_Counter = 0 65
54 Operation Theory 66
Operation Theory 55 67
Figure 4-20: Stop Mode I 67
56 Operation Theory 68
Figure 4-21: Stop Mode II 68
Figure 4-22: Stop Mode III 68
4.3 Digital I/O 69
58 Operation Theory 70
Figure 4-23: Mode 1 Operation 70
Operation Theory 59 71
Figure 4-24: Mode 2 Operation 71
60 Operation Theory 72
Figure 4-25: Mode 3 Operation 72
Figure 4-26: Mode 4 Operation 72
Operation Theory 61 73
Figure 4-27: Mode 5 Operation 73
Figure 4-28: Mode 6 Operation 73
62 Operation Theory 74
Figure 4-29: Mode 7 Operation 74
Figure 4-30: Mode 8 Operation 74
4.5 Trigger Sources 75
Operation Theory 65 77
66 Operation Theory 78
Operation Theory 67 79
68 Operation Theory 80
DAQ timing signals 81
72 Operation Theory 84
74 Operation Theory 86
AI_Trig_Out and AO_Trig_Out 87
76 Operation Theory 88
5 Calibration 89
5.2 Auto-calibration 90
Warranty Policy 91
80 Warranty Policy 92

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