Adlink DAQe-2006 Manual do Utilizador descarregar pdf (Página 85)

Operation Theory 73

In PCI form factor, there is a connector on the top right corner of

the card for the SSI. Refer to section 2.3 for the connector posi-

tion. All the SSI signals are routed to the 20-pin connector from the

FPGA. To synchronize multiple cards, users can connect a special

ribbon cable (ACL-SSI) to all the cards in a daisy-chain configura-

tion.

In PXI form factor, we utilize the PXI trigger bus built on the PXI

backplane to provide the necessary timing signal connections. All

the SSI signals are routed to the P2 connector. No additional cable

is needed. For detailed information of the PXI specifications, refer

to the PXI Specification Revision 2.0 from PXI System Alliance

(www.pxisa.org).

SSI timing signal Functionality

SSI_TIMEBASE

SSI master: send the TIMEBASE out

SSI slave: accept the SSI_TIMEBASE to

replace the internal TIMEBASE signal.

Note: Affected on both A/D and D/A

operations

SSI_AD_TRIG

SSI master: send the internal AD_TRIG out

SSI slave: accept the SSI_AD_TRIG as the

digital trigger signal.

SSI_ADCONV

SSI master: send the ADCONV out

SSI slave: accept the SSI_ADCONV to

replace the internal ADCONV signal.

SSI_SCAN_START

SSI master: send the SCAN_START out

SSI slave: accept the SSI_SCAN_START to

replace the internal SCAN_START signal.

SSI_DA_TRIG

SSI master: send the DA_TRIG out.

SSI slave: accept the SSI_DA_TRIG as the

digital trigger signal.

SSI_DAWR

SSI master: send the DAWR out.

SSI slave: accept the SSI_DAWR to replace

the internal DAWR signal.

Table 4-10: SSI Timing Signals Functionalities

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 91 92

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Adlink DAQe-2006 Manual do Utilizador Página 85